1. Field of the Invention
The present invention relates to a semiconductor device and method of fabricating thereof, in detail, further relates to the technology of a lateral double-diffused (LD) MOS transistor as a high-voltage device utilized for IC for driving a liquid crystal and others.
2. Description of the Related Art
In LD MOS transistor structure, a new diffusion region is formed by diffusing impurities the respective conductive types of which are different into a diffusion region formed on the side of the surface of a semiconductor substrate so as to utilize difference in diffusion in a lateral direction between these diffusion regions for effective channel length, and the corresponding device becomes a device suitable for reducing on-state resistance because a short channel is formed.
FIG. 20 is a sectional view for explaining a conventional type LD MOS transistor and for an example, N-channel LD MOS transistor structure is shown. Though the description of P-channel LD MOS transistor structure is omitted, the structure is similar as well known because it is different from the N-channel LD MOS transistor structure in only a conductive type.
As shown in FIG. 20, a reference number 1 denotes a semiconductor substrate the conductive type of which is a P type for example, 2 denotes an N-type well region, when a P-type body (PB) region 3 is formed in the N-type well region 2, an N+-type diffusion region 4 is formed in the P-type body region 3 and an N+-type diffusion region 5 is formed in the N-type well region 2. A gate electrode 7 is formed on the surface of the substrate via a gate insulating film 6 and a channel region 8 is formed in the superficial region of the P-type body region 3 immediately under the gate electrode 7.
The N+-type diffusion region 4 functions as a source region, the N+-type diffusion region 5 functions as a drain region and the N-type well region 2 formed from an region under the gate electrode 7 so that it surrounds the drain region functions as a drift region. S and D respectively denote a source electrode and a drain electrode, a reference number 12 denotes a P+-type diffusion region for applying electric potential to the P-type body region 3 and 11 denotes a layer insulation film.
In the LD MOS transistor, the concentration in the superficial region of the N-type well region 2 is increased by diffusing impurities into the N-type well region 2, current easily flows in the superficial region of the N-type well region 2 and withstand voltage can be enhanced. The LD MOS transistor composed as described above is called a reduced surface field type (RESURF) LD MOS transistor and the dopant concentration in the drift region of the N-type well region 2 is set so that it meets a RESURF condition. Such technique is disclosed in JP-A-9-139438 and others.
However, as the N-type well region 2 shown in FIG. 20 is formed so that it evenly has the same depth, it prevents the enhancement of withstand voltage and the reduction of on-state resistance region from being accelerated.
Therefore, the invention provides a semiconductor device that can meet a demand for enhancing withstand voltage and reducing on-state resistance and enables the further enhancement of withstand voltage by further optimizing the fabricating method.
In order to perform the above object, the method according to the invention to achieve the object is a method of fabricating a semiconductor device has a gate electrode formed on the semiconductor substrate via first and second gate insulating films whose thickness are different from each other, and a step of forming the drift region comprises a step of doping ions so that said drift region is formed so that depth is thin under the gate electrode and thick near drain region, by utilizing difference in a diffusion coefficient between at least two types of the same conductive type of impurities different in a diffusion coefficient and reverse conductive type of impurities having a diffusion coefficient substantially equal to or exceeding the diffusion coefficient of the one type of impurities of the two types of impurities
The fabricating method of a semiconductor device is characterized in that a process for forming a drift region is composed of a step for implanting at least two types of second conductive type impurities different in a diffusion coefficient into the surface layer of a substrate, a step for forming a first gate insulating film and a element isolation film by selective oxidation and respectively diffusing at least the two types of second conductive type impurities and a step for implanting and diffusing at least one type of first conductive type impurities having a diffusion coefficient approximately equal to or exceeding the diffusion coefficient of at least one type of second conductive type impurities, and in the step for forming the first gate insulating film and the element isolation film by selective oxidation in a state in which an oxide film and a polycrystalline silicon film or an oxide film and an amorphous silicon film are laminated on the substrate, only an region in which the drift region is formed is selectively oxidized in a state in which the polycrystalline silicon film or the amorphous silicon film is removed in a state, and the concentration of impurities in the drift region in the surface layer of the substrate can be reduced by suitably doping impurities implanted into the drift region formation region in the first gate insulating film when the first gate insulating film is formed.
A semiconductor device of the present invention is characterized in that said drift region is formed so that depth is thin under the gate electrode and thick near drain region, and said drift region is formed so that impurity concentration in said drift region under the first gate insulating film is lower than that under the second gate insulating film whose thickness is thinner than that of the first insulating film.
According the above device, impurity for example arsenic ions are prevented from being diffused in the substrate for the while, the decrease of the concentration of the arsenic ions under the first gate insulating film (selective oxide film 9A) was not enough, the concentration of the first Nxe2x88x92 layer 22A under the selective oxide film 9 become high and operating withstand voltage decreased because of electrostatic focusing.